A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage

Khayrollah HADIDI  Masahiro SASAKI  Tadatoshi WATANABE  Daigo MURAMATSU  Takashi MATSUMOTO  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.2   pp.261-266
Publication Date: 2000/02/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
sample-and-hold,  S/H,  full CMOS S/H,  open-loop S/H,  CMOS buffers,  

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Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 µm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.