A Phase Compensation Technique without Capacitors for the CMOS Circuit with a Very Low Impedance Terminal

Eitake IBARAGI  Akira HYOGO  Keitaro SEKINE  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.2   pp.236-242
Publication Date: 2000/02/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
analog signal processing,  MOS analog circuit,  phase compensation,  low impedance,  

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Summary: 
A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. Thus, the CMOS circuit with a very low impedance terminal (VLIT circuit) is a useful analog building block to achieve the above purpose. The very low impedance terminal in the VLIT circuit is performed by a shunt-series feedback configuration. However, the feedback generates a problem of instability and/or oscillation at the same time. The problem can be removed by a phase compensation capacitor as known well, but the capacitor is not desirable for integrated circuits due to its large area. This paper proposes a new phase compensation technique for the VLIT circuit. The proposed technique does not need any capacitors to obtain a sufficient phase margin, and instead gives us the appropriate transistor sizes (Width and length of the gate). As a result, the VLIT circuit has an enough phase margin and operates stably.