Optimized Software Implementations of E2

Kazumaro AOKI  Hiroki UEDA  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.1   pp.101-105
Publication Date: 2000/01/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Cryptography and Information Security)
Category: 
Keyword: 
E2,  SPN,  optimization,  32-bit processor,  64-bit processor,  inverse,  

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Summary: 
This letter describes several techniques for optimizing software implementations of E2 on various platforms. We propose optimization techniques for each part of E2; a new inversion algorithm, efficient byte splitting and merging for BP-Function, and an efficient SPN (Substitution-Permutation Network) implementation for 32- or 64-bit processors. As a result, E2 achieves the encryption speeds of 100.5 kb/s, 68.3 Mb/s, 162.3 Mb/s, and 130.8 Mb/s for H8/300 (5 MHz), Pentium Pro (200 MHz), Pentium II (450 MHz), and 21164A (600 MHz).