Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture

Chung-Hsin LIU  Nen-Fu HUANG  Chiou-Yng LEE  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A   No.12   pp.2657-2663
Publication Date: 2000/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
inner product,  cyclic shifting,  bit-parallel cellular array multipliers,  irreducible AOP,  canonical basis,  

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This study presents two new bit-parallel cellular multipliers based on an irreducible all one polynomial (AOP) over the finite field GF(2m). Using the property of the AOP, this work also presents an efficient algorithm of inner-product multiplication for computing AB2 multiplications is proposed, with a structure that can simplify the time and space complexity for hardware implementations. The first structure employs the new inner-product multiplication algorithm to construct the bit-parallel cellular architecture. The designed multiplier only requires the computational delays of (m+1)(TAND+TXOR). The second proposed structure is a modification of the first structure, and it requires (m+2) TXOR delays. Moreover, the proposed multipliers can perform A2iB2j computations by shuffling the coefficients to make i and j integers. For the computing multiplication in GF(2m), the novel multipliers turn out to be efficient as they simplify architecture and accelerate computation. The two novel architectures are highly regular, simpler, and have shorter computation delays than the conventional cellular multipliers.