Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition

Kazutoshi KOBAYASHI  Masanao YAMAOKA  Yukifumi KOBAYASHI  Hidetoshi ONODERA  Keikichi TAMARU  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E83-A    No.12    pp.2400-2408
Publication Date: 2000/12/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
VLSI,  functional memory,  DRAM,  parallel processor,  block matching,  

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We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.