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Easily Testable Realization Based on Single-Rail-Input OR-AND-EXOR Expressions
Takashi HIRAYAMA Goro KODA Yasuaki NISHITANI Kensuke SHIMIZU
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/09/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
logic synthesis, exclusive-or, single stuck-at fault, easily testable realization,
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It is known that AND-EXOR two-level networks obtained by AND-EXOR expressions with positive literals are easily testable. They are based on the single-rail-input logic, and require (n+4) tests to detect their single stuck-at faults, where n is the number of the input variables. We present three-level networks obtained from single-rail-input OR-AND-EXOR expressions and propose a more easily testable realization than the AND-EXOR networks. The realization is an OR-AND-EXOR network which limits the fan-in of the AND and OR gates to n/r and r respectively, where r is a constant (1 r n). We show that only (r+n/r) tests are required to detect the single stuck-at faults by adding r extra variables to the network.