IEICE Trans - Design of Multiple-Valued Programmable Logic Array with Unary Function Generators

Design of Multiple-Valued Programmable Logic Array with Unary Function Generators

Yutaka HATA  Naotake KAMIURA  Kazuharu YAMATO

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E82-D   No.9   pp.1254-1260
Publication Date: 1999/09/25
Online ISSN:
DOI:
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer Hardware and Design
Keyword:
multiple-valued logic,  programmable logic array,  unary function,  logic design,  minimization,

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Summary:
This paper describes the benefit of utilizing the unary function generators in a multiple-valued Programmable Logic Array (PLA). We will clarify the most suitable PLA structure in terms of the array size. The multiple-valued PLA considered here has a structure with two types of function generators (literal and unary function generators), a first-level array and a second-level array. On investigating the effectiveness to reduce the array size, we can pick up four form PLAs: MAX-of-TPRODUCT form, MIN-of-TSUM form, TSUM-of-TPRODUCT form and TPRODUCT-of-TSUM form PLAs among possible eight form PLAs constructing from the MAX, MIN, TSUM and TPRODUCT operators. The upper bound of the array sizes with v UGs is derived as (

pv + p(n-v) + 1) p^n-1 to realize any n-variable p-valued function. Next, experiments to derive the smallest array sizes are done for 10000 randomly generated functions and 21 arithmetic functions. These results conclude that MAX-of-TPRODUCT form PLA is the most useful in reducing the array size among the four form PLAs.