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Testing for the Programming Circuit of SRAM-Based FPGAs
Hiroyuki MICHINISHI Tokumi YOKOHIRA Takuji OKAMOTO Tomoo INOUE Hideo FUJIWARA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/06/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
fault detection, LUT-based FPGA, SRAM-based FPGA, functional fault, configuration,
Full Text: PDF(608.4KB)>>
The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.