Testing for the Programming Circuit of SRAM-Based FPGAs

Hiroyuki MICHINISHI  Tokumi YOKOHIRA  Takuji OKAMOTO  Tomoo INOUE  Hideo FUJIWARA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E82-D   No.6   pp.1051-1057
Publication Date: 1999/06/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
Keyword: 
fault detection,  LUT-based FPGA,  SRAM-based FPGA,  functional fault,  configuration,  

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Summary: 
The programming circuit of SRAM-based FPGAs consists of two shift registers, a control circuit and a configuration memory (SRAM) cell array. Because the configuration memory cell array can be easily tested by conventional test methods for RAMs, we focus on testing for the shift registers. We first derive test procedures for the shift registers, which can be done by using only the faculties of the programming circuit, without using additional hardware. Next, we show the validness of the test procedures. Finally, we show an application of the test procedures to test Xilinx XC4025.