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Power Estimation and Reduction of CMOS Circuits Considering Gate Delay
Hiroaki UEDA Kozo KINOSHITA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/01/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Computer Systems
CMOS circuit, low power design, gate delay, transition probability, switching activity,
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In this paper, we propose a method, called PORT-D, for optimizing CMOS logic circuits to reduce the average power dissipation. PORT-D is an extensional method of PORT. While PORT reduces the average power dissipation under the zero delay model, PORT-D reduces the average power dissipation by taking into account of the gate delay. In PORT-D, the average power dissipation is estimated by the revised BDD traversal method. The revised BDD traversal method calculates switching activity of gate output by constructing OBDD's without representing switching condition of a gate output. PORT-D modifies the circuit in order to reduce the average power dissipation, where transformations which reduce the average power dissipation are found by using permissible functions. Experimental results for benchmark circuits show PORT-D reduces the average power dissipation more than the number of transistors. Furthermore, we modify PORT-D to have high power reduction capability. In the revised method, named PORT-MIX, a mixture strategy of PORT and PORT-D is implemented. Experimental results show PORT-MIX has higher power reduction capability and higher area optimization capability than PORT-D.