A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive

Jin-Cheon KIM  Sang-Hoon LEE  Hong-June PARK  

IEICE TRANSACTIONS on Electronics   Vol.E82-C   No.9   pp.1777-1779
Publication Date: 1999/09/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Integrated Electronics
CMOS flip-flop,  low power,  half-swing clocking,  complementary drive,  

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A half-swing clocking scheme with a complementary gate and source drive is proposed for a CMOS flip-flop to reduce the power consumption of the clock system by 43%, while keeping the flip-flop delay time the same as that of the conventional full-swing clocking scheme. The delay time of the preceding half stage of a flip-flop using this scheme is less than half of that using the previous half-swing clocking scheme.