Low-Power Scheme of NMOS 4-Phase Dynamic Logic

Bao-Yu SONG  Makoto FURUIE  Yukihiro YOSHIDA  Takao ONOYE  Isao SHIRAKAWA  

IEICE TRANSACTIONS on Electronics   Vol.E82-C   No.9   pp.1772-1776
Publication Date: 1999/09/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section LETTER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Low-Power Circuit Technique
low power,  4-phase dynamic logic,  short-circuit current,  small voltage swing,  

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An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.