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Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology
Akira NAKADA Masahiro KONDA Tatsuo MORIMOTO Takemi YONEZAWA Tadashi SHIBATA Tadahiro OHMI
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
vector quantization, winner-take-all, neuron MOS, image compression, analog LSI,
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An analog vector quantization processor has been designed based on the neuron-MOS (νMOS) technology. In order to achieve a high integrating density, template information is merged into the matching cell (the absolute value circuitry) using the νMOS ROM technology. A new-architecture νMOS winner-take-all (WTA) circuit is employed for fully-parallel search for the minimum-distance vector. The WTA performs multi-resolution winner search with an automatic feedback gain control. A test chip having 256 16-element fixed template vectors has been built in a 1.5-µm double-polysilicon CMOS technology with the chip size of 7.2 mm 7.2 mm, and the basic operation of the circuits has been demonstrated.