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A Design Hierarchy of IC Interconnects and Gate Patterns
Shinji ODANAKA Akio MISAKA Kyoji YAMASHITA
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
TCAD, interconnect, OPC, gate pattern, design rule,
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A new design hierarchy in TCAD is discussed with emphasis on a design of IC interconnects and gate patterns. Two design methodologies for gate patterns at a CMOS cell level and multilevel interconnect scheme at a chip level are proposed. This approach generates the layout design rules of gate patterns, considering the fabrication process and pattern layout dependency, and allows a design of multilevel interconnect scheme at the initial phase of technology development.