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Two-Dimensional Cyclic Bias Device Simulator and Its Application to GaAs HJFET Pulse Pattern Effect Analysis
Yuji TAKAHASHI Kazuaki KUNIHIRO Yasuo OHNO
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on TCAD for Semiconductor Industries)
device simulation, cyclic bias simulator, pulse pattern effect, deep level, GaAs HJFET,
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A device simulator that simulates device performance in the cyclic bias steady state was developed, and it was applied to GaAs hetero-junction FET (HJFET) pulse pattern effect. Although there is a large time-constant difference between the pulse signals and deep trap reactions, the simulator searches the cyclic bias steady states at about 30 iterations. A non-linear shift in the drain current level with the mark ratio was confirmed, which has been estimated from the rate equation of electron capture and emission based on Shockley-Read-Hall statistics for deep traps.