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3-D Topography and Impurity Integrated Process Simulator (3-D MIPS) and Its Applications
Masato FUJINAGO Tatsuya KUNIKIYO Tetsuya UCHIDA Eiji TSUKUDA Kenichiro SONODA Katsumi EIKYU Kiyoshi ISHIKAWA Tadashi NISHIMURA Satoru KAWAZU
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on TCAD for Semiconductor Industries)
LSI fabrication, process simulator, topography, impurity diffusion, segregation, capacitance,
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We have developed a practical 3-D integrated process simulator (3-D MIPS) based on the orthogonal grid. 3-D MIPS has a 3-D topography simulator (3-D MULSS) and 3-D impurity simulator which simulates the processes of ion implantation, impurity diffusion and oxidation. In particular, its diffusion and segregation model is new and practical. It assumes the continuity of impurity concentration at the material boundary in order to coordinate with the topography simulator (3-D MULSS) with cells in which two or more kinds of materials exist. And then, we introduced a time-step control method using the Dufort-Frankel method of diffusion analysis for stable calculation, and a selective oxidation model to apply to more general structures than LOCOS structure. After that, the 3-D MIPS diffusion model is evaluated compared with experimental data. Finally, the 3-D MIPS is applied to 3-D simulations of the nMOS Tr. structure with LOCOS isolation, wiring interconnect and pn-junction capacitances, and DRAM storage node area.