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Mechanical Stress Simulation for Highly Reliable Deep-Submicron Devices
Hideo MIURA Shuji IKEDA
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
semiconductor, transistor, residual stress, stress analysis, stress measurement,
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We have improved the mechanical reliability of deep-submicron semiconductor devices by applying a simulation technique. Typical kinds of damages that reduce the reliability are dislocations in silicon substrates, delamination or cracking of thin films, and deterioration of electronic characteristics of devices. The mechanical stress that develops in device structures is caused by not only mismatches in thermal expansion coefficients among thin film materials but also intrinsic stress of thin films such as poly-silicon and silicides. Fine patterning by dry etching makes sharp edges and they also cause stress concentration and thus high stress. The manufacturing processes in which stress mainly develops are isolation, gate formation, and interconnect formation. We have developed methods for reducing the stress in each of the above-mentioned process. This stress reduction is very effective for highly reliable manufacturing. Finally, we clarify the effect of the residual stress in transistor structures on shift in the electronic characteristics of MOS transistors.