Advanced Characterization Method for Sub-Micron DRAM Cell Transistors

Ikuo KURACHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E82-C   No.4   pp.618-623
Publication Date: 1999/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
DRAM,  cell transistors,  test structure,  parameter extraction,  parasitic resistance,  

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Summary: 
An advanced characterization method for sub-micron DRAM cell transistors has been proposed for the analysis of transistor test structures using memory cell patterns. When the actual memory cell layout is used as a test structure, the parasitic source and drain resistance of the test structure affected conventional transistor parameters such as threshold voltage. To solve this problem, reduced drain current measurement methods have been proposed to suppress the parasitic resistance voltage drop. In these measurements, two new transistor parameters, Vgoff and Vgsat, have been proposed which are related to off-leakage and full writing, respectively. These parameters are found to be good parameters for monitoring DRAM bit failures. A new threshold voltage measurement methodology has also been proposed for test structures with high parasitic resistance.