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Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI
Tetsuhisa MIDO Hiroshi ITO Kunihiro ASADA
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures)
test structure, capacitance matrix, VLSI interconnection, shift registers, non-overlap clock signal, sub-femto-farad measurement,
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A compact new test structure using shift register circuits for extracting components of the capacitance matrix of the multi-layer interconnections has been proposed. An extraction method of the capacitance matrix is also presented. As a result of fabrication, capacitance values obtained by measurement are in good agreement with the numerical calculation. We also showed an estimation method of the measurement errors.