Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM

Fukashi MORISHITA  Yasuo YAMAGUCHI  Takahisa EIMORI  Toshiyuki OASHI  Kazutami ARIMOTO  Yasuo INOUE  Tadashi NISHIMURA  Michihiro YAMADA  

IEICE TRANSACTIONS on Electronics   Vol.E82-C    No.3    pp.544-552
Publication Date: 1999/03/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
SOI-DRAM,  floating body,  high speed,  low power,  data retention characteristics,  

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It is confirmed by simulation that SOI-DRAMs can be operated at high speed by using the floating body structures. Several floating body effects are analyzed. It is described that the dynamic retention characteristics are not dominated by capacitive coupling and hole redistribution. And it is described that those characteristics are determined by the leakage current in the small pn-junction region of the floating body. Reducing pn junction leakage current is important for realizing a long retention time. If the pn junction leakage is suppressed to 10-18 A/µm, a dynamic retention time of 520 sec at a VBSG of 0.5 V can be achieved at 27. On those conditions, the refresh current of SOI-DRAMs is reduced by 54% compared with bulk-Si DRAMs.