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Low-Power 2.5-Gb/s Si-Bipolar IC Chipset for Optical Receivers and Transmitters Using Low-Voltage and Adjustment-Free Circuit Techniques
Masaki HIROSE Keiji KISHINE Haruhiko ICHINO Noboru ISHIHARA
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
optical receiver, optical transmitter, adjustment free, Si bipolar, offset, PLL,
Full Text: PDF(1.1MB)>>
This paper describes a 2.5-Gb/s optical receiver and transmitter chipset consisting of a preamplifier, a main amplifier, a clock and data recovery (CDR) circuit, and a laser-diode (LD) driver. Low-voltage and adjustment-free circuit techniques are introduced in order to achieve low cost and low power circuits. Circuit adjustments are eliminated by using a multi-stage automatic offset canceling technique in the main amplifier, and by using a PLL structure with a sample-and-hold technique in the CDR circuit. For power reduction, ICs are operated at a power supply voltage of -3 V. Fabricating the ICs by a 0.5-µm Si bipolar process makes it possible to achieve 2.5-Gb/s receiver and transmitter operation with a total power dissipation of 1.04 W. Especially significant is that the receiver ICs need no external devices and adjustments.