|
For Full-Text PDF, please login, if you are a member of IEICE,
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
|
0.21-fJ GaAs DCFL Circuits Using 0.2-µm Y-Shaped Gate AlGaAs/InGaAs E/D-HJFETs
Shigeki WADA Masatoshi TOKUSHIMA Masaoki ISHIKAWA Nobuhide YOSHIDA Masahiro FUJII Tadashi MAEDA
Publication
IEICE TRANSACTIONS on Electronics
Vol.E82-C
No.3
pp.491-497 Publication Date: 1999/03/25 Online ISSN:
DOI: Print ISSN: 0916-8516 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Compound Semiconductor Devices Keyword: GaAs, heterojunction FET, Y-shaped gate, DCFL, low supply voltage,
Full Text: PDF>>
Summary:
Ultra-low-power-consumption and high-speed DCFL circuits have been fabricated by using 0.2-µm Y-shaped gate E/D-heterojunction-FETs (HJFETs) with a high-aspect-ratio gate-structure, which has an advantage of reducing the gate-fringing capacitance (Cf) to about a half of that of a conventional low-aspect-ratio one. A fabricated 51-stage ring oscillator with the 0.2-µm Y-shaped gate n-AlGaAs/i-InGaAs E/D-HJFETs shows the lowest power-delay product of 0.21 fJ with an unloaded propagation delay of 34.9 ps at a supply voltage (VDD) of 0.4 V. We also analyze the DCFL switching characteristics by taking into account the intrinsic gate-to-source capacitance (Cgsint) and the Cf. The analysis results for the power-delay products agree well with our experimental results. Our analysis also indicates the DCFL circuit with the high-aspect-ratio Y-shaped gate E/D-HJFETs can reduce the power-delay products by 35% or more below 0.25-µm gate-length as compared to conventional ones with the low-aspect-ratio Y-shaped gate HJFETs. These results clarify that the Cf-reduction of the Y-shaped gate HJFETs is more effective in improving the power-delay products than reducing the gate-length.
|
|
|