Design Innovations for Multi-Gigahertz-Rate Communication Circuits with Deep-Submicron CMOS Technology

Masakazu KURISU  Muneo FUKAISHI  Hiroshi ASAZAWA  Masato NISHIKAWA  Kazuyuki NAKAMURA  Michio YOTSUYANAGI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E82-C   No.3   pp.428-437
Publication Date: 1999/03/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: 
Keyword: 
CMOS,  deep-submicron,  communication,  Gigahertz,  

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Summary: 
In this paper, we briefly review the recent research on CMOS gigahertz-rate communication circuits. Then, we describe design innovations we have made to overcome limitations on communication speed. Using 0. 25-µm CMOS technology, we developed a 4.25-Gb/s Fibre Channel transceiver that features an asynchronous tree-type 1 : 8 demultiplexer and an 8-bit-to-10-bit frequency-conversion architecture. And using 0. 15-µm CMOS technology, we developed an 11. 8-GHz frequency divider that introduces the novel idea of a hysteresis-controlled latch (HC-latch). With these results, we discuss high-speed LSI design issues and future prospects.