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A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs
Shin CHAKI Yoshinobu SASAKI Naoto ANDOH Yasuharu NAKAJIMA Kazuo NISHITANI
IEICE TRANSACTIONS on Electronics
Publication Date: 1999/11/25
Print ISSN: 0916-8516
Type of Manuscript: INVITED PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century)
Category: Low Power-Consumption RF ICs
MMIC, circuit design, miniaturization, layout optimization, electromagnetic analysis, SAMFET, LNA,
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This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.