A New Digitized Bit Timing Recovery Scheme Using a Perturbed Sample Timing Technique for High-Bit-Rate Wireless Systems

Toshiaki TAKAO  Yoshifumi SUZUKI  Tadashi SHIRATO  

Publication
IEICE TRANSACTIONS on Communications   Vol.E82-B   No.8   pp.1326-1333
Publication Date: 1999/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Communication Device and Circuit
Keyword: 
bit timing recovery,  multimedia communication,  wireless access,  perturbed sample timing technique,  

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Summary: 
We propose a new bit timing recovery (BTR) scheme, called perturbed sampling BTR (PSBTR), that can operate near the symbol rate in high-bit-rate wireless systems. A peculiar sample clock, the duty factor of which is not 50%, is used in the PSBTR scheme. We call this type of clock a perturbed sample clock and use it for clock recovery. In PSBTR, there is no cycle slip of the sample clock, and the PSBTR circuit is mostly digital. We examine the performance of the PSBTR scheme under additive white Gaussian noise (AWGN) by computer simulation and experiment, and from these results, clarify the relationship between the performance and circuit parameters of the PSBTR circuit. The overall results indicate that the PSBTR scheme performs well and can be employed as a BTR scheme for high-bit-rate wireless systems.