A 10-Gb/s Optical Asynchronous Packet Receiver with a Fast Bit-Synchronization Circuit

Akio TAJIMA  Hiroaki TAKAHASHI  Yoshiharu MAENO  Soichiro ARAKI  Naoya HENMI  

Publication
IEICE TRANSACTIONS on Communications   Vol.E82-B   No.8   pp.1121-1126
Publication Date: 1999/08/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Joint Special Issue on Recent Progress in Optoelectronics and Communications)
Category: Communication Networks
Keyword: 
optical packet switch,  bit synchronization,  asynchronous packet receiver,  

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Summary: 
A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.