IEICE Trans - PLL Frequency Synthesizer with Multi-Phase Detector

PLL Frequency Synthesizer with Multi-Phase Detector

Yasuaki SUMI  Kouichi SYOUBU  Shigeki OBOTE  Yutaka FUKUI  Yoshio ITOH

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E82-A   No.3   pp.431-435
Publication Date: 1999/03/25
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
PLL frequency synthesizer,  multi-phase detector,  speedup of lock up time,

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Summary:
The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then, a higher speed lock-up time and good spurious characteristics can be achieved.