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SCR : SPICE Netlist Reduction Tool
Mototaka KURIBAYASHI Masaaki YAMADA Hideki TAKEUCHI Masami MURAKATA
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
SPICE, reduction, transistor, simulation, CAD, VLSI,
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This paper describes an efficient SPICE netlist reduction method, which enables collective simulation of large circuits. The method reduces a SPICE netlist to only those devices which affect the simulation results. Parts of the netlist can be significantly reduced in size, with relatively discrepancies arising between the original SPICE simulation and the reduced SPICE simulation. The authors' reduction method is more general than previous works, since it reduces circuits using the features of MOS transistors. According to experimental results, reduction rates can range from 1/2 to 1/223. Depending on the reduction, the time taken time to run a SPICE simulation was reduced by between one and two oder of magnitude. Using this method and working on the reduced netlist, SPICE could even handle netlist for very large circuits which it could not ordinarily handle. The simulation error between the original SPICE simulation and the reduced SPICE simulation was about 3.5%.