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Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell
Changku HWANG Akira HYOGO Hong-sun KIM Mohammed ISMAIL Keitaro SEKINE
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
analog signal processing, CMOS, low voltage, composite transistor, multiplier,
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A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |Vt|+2 Vds,sat and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2µm N-well process with a 3 V supply are given.