Parallel Test Structure in Latch Based Asynchronous Pipeline

Jing-ling YANG  Chiu-sing CHOY  Cheong-Fat CHAN  

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E82-A   No.11   pp.2527-2529
Publication Date: 1999/11/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
asynchronous,  pipeline,  event logic,  latch,  test,  

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Summary: 
Detecting the stuck-at-pass faults in the event-driven latches is the main difficult in testing latch based asynchronous pipeline. In this paper we proposed a parallel test structure to ease this problem.