For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Parallel Test Structure in Latch Based Asynchronous Pipeline
Jing-ling YANG Chiu-sing CHOY Cheong-Fat CHAN
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Print ISSN: 0916-8508
Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
asynchronous, pipeline, event logic, latch, test,
Full Text: PDF(468.5KB)>>
Detecting the stuck-at-pass faults in the event-driven latches is the main difficult in testing latch based asynchronous pipeline. In this paper we proposed a parallel test structure to ease this problem.