IEICE Trans - A New Single-Clock Flip-Flop for Half-Swing Clocking

A New Single-Clock Flip-Flop for Half-Swing Clocking

Young-Su KWON  In-Cheol PARK  Chong-Min KYUNG

Publication
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E82-A   No.11   pp.2521-2526
Publication Date: 1999/11/25
Online ISSN:
DOI:
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
low power circuit,  clocking power,  half-swing clocking,

Full Text: PDF>>

Summary:
A new flip-flop configuration for half-swing clocking is proposed to save total clocking power. In the proposed scheme, only NMOS's are clocked with the half-swing clock in order to make it operate without level converters or any additional logics which were used in the earlier half-swing clocking schemes. V_cc is supplied to the random logic circuits and flip-flops while V_cc/2 is supplied to the clock network and some parts of the flip-flop to reduce the power consumed in the clock network. Compared to the conventional scheme, the proposed flip-flop configuration can save the clocking power by 40%.