Simplified Routing Procedure for a CAD-Verified FPGA

Takahiro MUROOKA  Atsushi TAKAHARA  Toshiaki MIYAZAKI  

IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences   Vol.E82-A   No.11   pp.2440-2447
Publication Date: 1999/11/25
Online ISSN: 
Print ISSN: 0916-8508
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
FPGA,  CAD algorithms,  routing,  

Full Text: PDF(1MB)>>
Buy this Article

The design of high performance-circuits using Field-Programmable Gate Arrays (FPGAs) requires a balance between the FPGA's architecture and CAD algorithms. Conventional FPGAs and CAD algorithms are developed independently, which makes it difficult to implement application circuits. To solve this problem, we developed a CAD-verified FPGA whose architecture was designed at the same time as the CAD algorithms. This paper shows how a CAD-verified FPGA architecture can simplify a routing algorithm. The algorithm is studied in terms of computational complexity and is simplified using the properties of our FPGA (switch module structure and the number of routing resources). The routing algorithm is almost one hundred times faster than that of the conventional router, and the quality of its circuits is also improved.