IEICE Trans - Transistor Leakage Fault Diagnosis for CMOS Circuits

Transistor Leakage Fault Diagnosis for CMOS Circuits

Xiaoqing WEN
Hideo TAMAMOTO
Kewal K. SALUJA
Kozo KINOSHITA

Publication
IEICE TRANSACTIONS on Information and Systems Vol.E81-D No.7 pp.697-705
Publication Date: 1998/07/25
Online ISSN:
DOI:
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword:
fault diagnosis, transistor leakage fault, I_DDQ, primary output, fault simulation, diagnostic test generation,

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Summary:
This paper presents a new methodology for diagnosing transistor leakage faults in a CMOS circuit by using both I_DDQ and logic value information. A hierarchical procedure is used to identify and delete impossible fault candidates efficiently and a procedure is employed to generate diagnostic tests for improving diagnostic resolution. A novel approach for handling the intermediate output voltage of a faulty gate is used in new methods for fault simulation and diagnostic test generation based on primary output values. Experimental results on ISCAS

85 circuits show the effectiveness of the proposed methodology.