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Test Generation for Sequential Circuits under IDDQ Testing
Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
sequential circuit, test generation, IDDQ testing, bridging fault,
Full Text: PDF(707.5KB)>>
This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.