An Iterative Improvement Method for Generating Compact Tests for IDDQ Testing of Bridging Faults

Tsuyoshi SHINOGI  Terumine HAYASHI  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E81-D   No.7   pp.682-688
Publication Date: 1998/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: IDDQ Testing
Keyword: 
compaction,  IDDQ testing,  iterative improvement method,  bridging fault,  ATPG,  

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Summary: 
IDDQ testing, or current testing, is a powerful method which detects a large class of defects which cause abnormal quiescent current, by measuring the power supply current. One of the problems on IDDQ testing which prevent its full practical use in manufacturing is that the testing speed is slow owing to time-consuming IDDQ measurement. One of the solutions to this problem is test pattern compaction. This paper presents an efficient method for generating a compact test set for IDDQ testing of bridging faults in combinational CMOS circuits. Our method is based on the iterative improvement method. Each of random primary input patterns is iteratively improved through changing its values pin by pin selected orderly, so as to increase the number of newly detected faults in the current yet undetected fault set. While our method is simple and easy to implement, it is efficient. Experimental results for large ISCAS benchmark circuits demonstrate its efficiency in comparison with results of previous methods.