On Acceleration of Test Points Selection for Scan-Based BIST

Michinobu NAKAO  Kazumi HATAYAMA  Isao HIGASHI  

IEICE TRANSACTIONS on Information and Systems   Vol.E81-D   No.7   pp.668-674
Publication Date: 1998/07/25
Online ISSN: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Built-in Self-Test
test points,  BIST,  optimization,  testability,  

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This paper presents an acceleration of test points selection for circuits designed by a full-scan based BIST scheme. In order to accelerate the test points selection based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed techniques and evaluate its efficiency experimentally using large scale circuits (26 k-420 k gates).