Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops

Toshinori HOSOKAWA  Toshihiro HIRAOKA  Mitsuyasu OHTA  Michiaki MURAOKA  Shigeo KUNINOBU  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E81-D   No.7   pp.660-667
Publication Date: 1998/07/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
design for testability,  partial scan design method,  n-fold line-up structure,  pure load/hold FF,  

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Summary: 
We will present a partial scan design method based on n-fold line-up structures in order to achieve high fault efficiency and reduce test pattern generation time for practical LSIs. We will also present a partial scan design method based on the state justification of pure load/hold FFs in order to achieve high fault efficiency and reduce the number of scan FFs for practical LSIs with lots of load/hold FFs. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency (more than 99%) and reduce the number of scan FFs for the LSI with lots of load/hold FFs.