For Full-Text PDF, please login, if you are a member of IEICE,|
or go to Pay Per View on menu list, if you are a nonmember of IEICE.
Improving Random Pattern Testability with Partial Circuit Duplication Approach
Hiroshi YOKOYAMA Xiaoqing WEN Hideo TAMAMOTO
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Print ISSN: 0916-8532
Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
partial circuit duplication, random testing, design for testability, built-in self-test,
Full Text: PDF>>
The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable due to the existence of random pattern resistant faults. In this paper, we present a method for improving the random pattern testability of logic circuits by partial circuit duplication approach. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.