Transistor Leakage Fault Diagnosis with IDDQ and Logic Information

Wen XIAOQING  Hideo TAMAMOTO  Kewal K. SALUJA  Kozo KINOSHITA  

Publication
IEICE TRANSACTIONS on Information and Systems   Vol.E81-D   No.4   pp.372-381
Publication Date: 1998/04/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
Keyword: 
fault diagnosis,  transistor leakage fault,  IDDQ testing,  fault simulation,  diagnostic vector generation,  

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Summary: 
This paper proposes a new methodology for diagnosing transistor leakage faults with information on IDDQ and logic values at primary output lines. A hierarchical approach is proposed to identify the faults that do not exist in the circuit through comparing their IDDQ and logic behaviors predicted by simulation with observed responses. Several techniques for handling intermediate faulty voltages in fault simulation are also proposed. Further, an approach is proposed to generate diagnostic vectors based on IDDQ information. In addition, a method for identifying IDDQ equivalent faults is proposed to reduce the time needed for diagnostic vector generation and to improve diagnostic resolution. Experimental results show that the proposed methodology often confines diagnosed faults to only a few gates.