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Fault-Tolerant Meshes with Efficient Layouts
Toshinori YAMADA Shuichi UENO
IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/01/25
Print ISSN: 0916-8532
Type of Manuscript: PAPER
Category: Fault Tolerant Computing
meshes, fault-tolerant graphs, embeddings, layouts, wire length,
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This paper presents a practical fault-tolerant architecture for mesh parallel machines that has t spare processors and has 2(t+2) communication links per processor while tolerating at most t+1 processor and link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most O(t).