A 300 MHz Dual Port Palette RAM Using Port Swap Architecture

Yasunobu NAKASE  Koichiro MASHIKO  Yoshio MATSUDA  Takeshi TOKUDA  

IEICE TRANSACTIONS on Electronics   Vol.E81-C       pp.1484-1490
Publication Date: 1998/09/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Category: Electronic Circuits
dual port SRAM,  graphics,  color palette,  small cell size,  

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This paper proposes a dual port color palette SRAM using a single bit line cell. Since the single bit line cell consists of fewer bit lines and transistors than standard dual port cells, it is able to reduce the area. However, the cell has had a problem in writing a high level. The port swap architecture solves the problem without any special mechanism such as a boot strap. In the architecture, each of two bit lines is assigned to the read/write MPU port and the read only pixel port, respectively. When writing a low level, the MPU port uses pre-assigned bit line. On the other hand, when writing a high level, the MPU port uses the bit line assigned to the pixel port by a swap operation. During the swapping, the pixel port continues the read operation by using the bit line assigned to the MPU port. A color palette using this architecture is fabricated with a 0. 5 µm CMOS process technology. The memory cell size reduces by up to 43% compared with standard dual port cells. The color palette is able to supply the pixel data at 300 MHz at the supply voltage of 3.3 V. This speed is enough to support the practical highest resolution monitors in the world.