Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs

Taku OHSAWA  Koji KAI  Kazuaki MURAKAMI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.9   pp.1455-1462
Publication Date: 1998/09/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DRAM,  DRAM refresh,  merged DRAM/logic,  system LSI,  low power,  

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Summary: 
In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.