A Reconfigurable Digital Signal Processor

Boon Keat TAN  Toru OGAWA  Ryuji YOSHIMURA  Kenji TANIGUCHI  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.9   pp.1424-1430
Publication Date: 1998/09/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DSP processor,  reconfigurable,  flexible,  processors array,  fault-tolerant,  ASIC,  digital signal processing,  RISC,  

Full Text: PDF>>
Buy this Article




Summary: 
This paper describes a new architecture-based DSP processor, which consists of n n mesh multiprocessor for digital signal processing. A prototype chip, RCDSP9701 has been designed and implemented using a CMOS 0. 6 µm process. This architecture has better performance compare to the traditional microprocessor solution to Digital Signal Processing. The proposed method poses remarkable flexibility compare to ASIC (Application Specified Integrated Circuits) approach for Digital Signal Processing applications. In addition, the proposed architecture is fault tolerant and suitable for parallel computing applications. In this paper, an implementation into a silicon chip of the new architecture is presented to give a better understanding of our work.