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A Real-Time MPEG2 Encoding and Decoding Architecture with a Dual-Issue RISC Processor
Akira YAMADA Toyohiko YOSHIDA Tetsuya MATSUMURA Shin-ichi URAMOTO Koji TSUCHIHASHI Edgar HOLMANN
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
multimedia processor, media processor, VLIW, MPEG, microprocessor,
Full Text: PDF(1005.9KB)>>
Integrating a 243 MHz dual-issue RISC processor core with a small set of dedicated hardware can create a single chip system for real-time encoding and decoding for MPEG2 MP@ML (main profile at main level). A trade-off between software and dedicated hardware is very important to decide performance of the system. This paper evaluates several MPEG2 encoding and decoding systems, focusing on both chip area and power consumption. For MPEG2 encoding, a newly introduced hybrid approach includes the processor core and the dedicated hardware that performs the discrete cosine transform (DCT), the inverse DCT (IDCT), variable length encoding (VLC) and block loading process. The estimated area for the encoder, 23. 0 mm2 using a 0. 3-micrometer 1-poly 4-metal CMOS process, is 33% smaller than that of the dedicated hardware approach. The estimated power consumption for the encoder is 13% smaller than that of the dedicated hardware approach. The dual-issue RISC processor approach has the advantage of a small chip area, low power consumption and that of being very easy to program for multimedia applications.