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A Dual-Issue RISC Processor for Multimedia Signal Processing
Hisakazu SATO Toyohiko YOSHIDA Masahito MATSUO Toru KENGAKU Koji TSUCHIHASHI
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
multimedia, DSP, microprocessor, VLIW,
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This paper presents the architecture of a newly-developed dual-issue RISC processor, D10V, that achieves both high throughput signal processing capability and maintains flexibility for general purpose applications. The RISC processor uses a 2-way VLIW architecture with a 32-bit wide instruction word. Two sub-instructions in a VLIW instruction are executed in two execution units in parallel. It also has several enhancements for signal processing. The processor includes pipelined multiply-and-accumulate instructions allowing a new multiply operation to be initiated every clock cycle and block repeat instructions for zero delay penalty loops. Single-cycle data moves of double-word data elements with modulo addressing are provided to deliver required memory bandwidth for signal processing applications. As a result, the D10V achieves high signal processing capability as 1 clock cycle per tap for FIR filtering. Also, several DSP benchmarks illustrate that the D10V competes favorably and in some instances outperforms conventional 16-bit DSPs. For master controlling application, the processor provides memory operations for signed/unsigned byte and bit wise operations. It shows 49 Dhrystone MIPS at 52 MHz, for general purpose applications.