An Analytical Toggle Frequency Expression for Source-Coupled FET Logic (SCFL) Frequency Dividers

Taiichi OTSUJI

IEICE TRANSACTIONS on Electronics   Vol.E81-C       pp.1106-1111
Publication Date: 1998/07/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: Category: Electronic Circuits
analytical expression,  toggle frequency,  SCFL,  frequency divider,  GaAs MESFET,  

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In order to develop high-speed ICs, it is important to clarify the relationship between circuit speed and device parameters. An analytical expression for circuit performance is effective for this purpose. This paper describes an analytical toggle frequency expression for Source-Coupled FET Logic (SCFL) frequency dividers. The proposed equation is expressed as the sum of the product of sensitivity coefficients of FET parameters and time constants which are extracted through a small signal transfer function analysis. These sensitivity coefficients are extracted using SPICE simulations. The equation is a simple formula with only five coefficients, which is much smaller than conventional sensitivity analyses. Furthermore, the accuracy of the proposed equation is improved compared to an analytical method based on the small signal transfer function which we previously proposed. The equation can be easily extended to consider interconnection delay time. The calculated maximum toggle frequencies using the equation show good agreement with SPICE simulations and experimental results for a wide gate-length variation range of 0. 12-µm to 0. 24-µm GaAs MESFETs. By re-extraction of another set of sensitivity coefficients, the proposed equation can be widely applied to shorter gate-length GaAs MESFETs and other FET devices such as HEMT devices. The expression clearly shows the relationship between the circuit performance and intrinsic FET parameters. According to the equation, the key parameters for high-speed circuit operation are high transconductance with a low drain conductance, and a low gate-drain capacitance. The equation can be used as a criterion for the optimization of the FET structure to realize high speed circuit performance.