Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM

Yoshiharu AIMOTO  Tohru KIMURA  Yoshikazu YABE  Hideki HEIUCHI  Youetsu NAKAZAWA  Masato MOTOMURA  Takuya KOGA  Yoshihiro FUJITA  Masayuki HAMADA  Takaho TANIGAWA  Hajime NOBUSAWA  Kuniaki KOYAMA  

Publication
IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.5   pp.759-767
Publication Date: 1998/05/25
Online ISSN: 
DOI: 
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
integration of DRAM and logic,  embedded DRAM,  low power,  high memory bandwidth,  

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Summary: 
We have developed a parallel image processing RAM (PIP-RAM) which integrates a 16-Mb DRAM and 128 processor elements (PEs) by means of 0. 38-µm CMOS 64-Mb DRAM process technology. It achieves 7. 68-GIPS processing performance and 3. 84-GB/s memory bandwidth with only 1-W power dissipation (@ 30-MHz), and the key to this performance is the DRAM design. This paper presents the key circuit techniques employed in the DRAM design: 1) a paged-segmentation accessing scheme that reduces sense amplifier power dissipation, and 2) a clocked low-voltage-swing differential-charge-transfer scheme that reduces data line power dissipation with the help of a multi-phase synchronization DRAM control scheme. These techniques have general importance for the design of LSIs in which DRAMs and logic are tightly integrated on single chips.