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5. 4 GOPS, 81 GB/s Linear Array Architecture DSP
Akihiko HASHIGUCHI Masuyoshi KUROKAWA Ken'ichiro NAKAMURA Hiroshi OKUDA Koji AOYAMA Mitsuharu OHKI Katsunori SENO Ichiro KUMATA Masatoshi AIKAWA Hirokazu HANAKI Takao YAMAZAKI Mitsuo SONEDA Seiichiro IWASE
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
video, parallel processing, SIMD, DSP,
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A programmable DSP with linear array architecture for real-time video processing is reported. It achieves a processing rate of 5. 4 GOPS and 81GB/s memory bandwidth using Dual Sense Amplifier architecture. A low-power-supply pipeline decreases power consumption and a time shared bit-line reduces chip area. It has 4320 processor elements and a 1. 1 Mbit 3-port memory. The DSP can be applied to HDTV signals with its 75 MHz peak I/O rate. Sufficient programmability is provided to execute video format conversion such as image size conversion and Y/C separation, and picture quality improvement such as noise reduction and image enhancement. The chip was fabricated using 0. 4 µm CMOS triple metal technology with a 15. 12 mm 14. 95 mm die. It operates at 50 MHz and consumes 0. 53 W/GOPS at 3. 3 V.