Application of Circuit-Level Hot-Carrier Reliability Simulation to Memory Design

Peter M. LEE  Tsuyoshi SEO  Kiyoshi ISE  Atsushi HIRAISHI  Osamu NAGASHIMA  Shoji YOSHIDA  

IEICE TRANSACTIONS on Electronics   Vol.E81-C   No.4   pp.595-601
Publication Date: 1998/04/25
Online ISSN: 
Print ISSN: 0916-8516
Type of Manuscript: PAPER
Category: Electronic Circuits
hot-carrier degradation,  reliability,  device lifetime,  circuit simulation,  SRAM,  DRAM,  

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We have applied hot-carrier circuit-level simulation to memory peripheral circuits of a few thousand to over 12K transistors using a simple but accurate degradation model for reliability verification of actual memory products. By applying simulation to entire circuits, it was found that the location of maximum degradation depended greatly upon circuit configuration and device technology. A design curve has been developed to quickly relate device-level DC lifetime to circuit-level performance lifetime. Using these results in conjunction with a methodology that has been developed to predict hot-carrier degradation early in the design cycle before TEG fabrication, accurate total-circuit simulation is applied early in the design process, making reliability simulation a crucial design tool rather than a verification tool as technology advances into the deep sub-micron high clock rate regime.