IEICE Trans - Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro

Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro

Kenichi OHHATA  Takeshi KUSUNOKI  Hiroaki NAMBU  Kazuo KANETANI  Keiichi HIGETA  Kunihiko YAMAGUCHI  Noriyuki HOMMA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E81-C       pp.447-454
Publication Date: 1998/03/25
Online ISSN:
DOI:
Print ISSN: 0916-8516
Type of Manuscript: Category: Integrated Electronics
Keyword:
high-speed SRAM,  ECL-CMOS SRAM,  write pulse generator,

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Summary:
We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.