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Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map
Kei EGUCHI Takahiro INOUE Akio TSUNEDA
IEICE TRANSACTIONS on Electronics
Publication Date: 1998/01/25
Print ISSN: 0916-8516
Type of Manuscript: LETTER
Category: Electronic Circuits
chaos circuits, digital circuits, discrete-time circuits, integrated circuits, FPGA,
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An econominal implementation of a chaos circuit onto the hardware is an important subject. In this letter, a two-dimensional digital chaos circuit realizing a Henon map is designed. Concerning the attractor and the bifurcation diagram of the proposed circuit, numerical simulations are performed to confirm the validity of the circuit algorithm. Furthermore, the proposed digital chaos circuit is designed by Verilog-HDL (Hardware Description Language). The proposed digital chaos circuit can be implemented into the form of the FPGA (Field Programmable Gate Array).